1. Field of the Invention
The present invention relates to a flat panel display apparatus and, more particularly, to a timing control circuit of a plasma display panel (PDP) television which generates clock signals to control input/output operations of a video data to/from a data interfacing circuit.
2. Description of the Prior Art
A PDP system can be classified into an alternating current (AC) type and a direct current (DC) type according to kinds of driving voltages being applied to discharge cells. In FIG. 1, a whole circuit configuration of an AC type PDP color television which relates to the present invention is illustrated. In the AC type PDP color television, a composite video signal received through an antenna is converted into a digital data by an analog-to digital converting section 12 after being processed by an audio/video signal processing section 10. Here, one frame of the composite video signal consists of two fields, that is, an even field and an odd field which are being interlaced, and a horizontal sync signal has a frequency of about 15.73 Khz and a vertical sync signal has a frequency of about 60 Hz. After being processed by a data processing section 14 which contains a data rearranging section 14a, a frame memory section 14b and a data interfacing section 14c, the digital data is transferred to address electrode driving sections 20 and 22 in a form of a data stream which is suitable to a gradation processing characteristic of the PDP television. A high voltage generating section 18 produces control pulses, which are needed for driving an PDP by upper and lower address electrode driving sections 20 and 22, a scan electrode driving section 24 and a sustain electrode driving section 26, and by combining direct high voltages according to logic levels of control pulses from a timing control section 16. A power supplying section 30 takes an AC voltage as an input power source and produces all the DC voltages being necessary for the whole PDP system. Upper address electrode driving section 20 applies address pulses to odd address electrode lines of a plasma panel 28 in responsive to high and low levels of red-green-blue (RGB) data provided by data interfacing section 14c, and lower address electrode driving section 22 applies address pulses to even address electrode lines of plasma panel 28 in responsive to the high and low levels of the RGB data provided by data interfacing section 14c. Being supplied with a DC high voltage from a high voltage generating section 18, scanning and sustaining sections 24 and 26 provide scanning and sustaining pulses to scanning and sustaining electrode lines of plasma panel 28, respectively. Timing controlling section 16 is supplied with the vertical and horizontal sync signals from audio/video signal processing section 10, produces a data reading clock to be supplied to data rearranging section 14a, frame memory section 14b and data interfacing section 14c, and also produces various logic control pulses to be supplied to high voltage driving section 18.
Generally, for the gradation processing of the PDP, the video data of one field should be rebuilt into multiple subfields and then be rearranged, based on a significance of respective data, in an order from the most significant bit to the least significant bit. Furthermore, prior to being used as a displaying data, the video data in an interlaced scanning way should be converted into a sequential scanning way. Accordingly, frame memory section 14b is used as a data storing area for holding the RGB video data of one frame.
Particularly, data interfacing section 14c implements cyclic operations of provisionally storing the RGB data of one horizontal line of plasma panel 28 transferred from frame memory 14b, rearranging the RGB data to be suitable for an pixel arrangement of plasma panel 28 and providing the rearranged RGB data to upper and lower address electrode driving sections 20 and 22. In order to rearrange the video data of the whole 480 horizontal lines of plasma panel 28 by a data amount of one horizontal line during an addressing time of one subfield, data interfacing section 14c has two provisional data storing sections that each of them can store the data amount of one horizontal line (853.times.3=2559 bits) supplied from frame memory 14b. The reason that data interfacing section 14c includes the two provisional data storing sections is to secure a continuity of data. Namely, for a smooth display of a moving picture, data interfacing section 14c simultaneously implements an input operation to receive the video data from frame memory 14b by using a first provisional data storing section and an output operation to transfer stored video data in a second provisional data storing section to address electrode driving sections 20 and 22.
In the simultaneous input/output operations of data interfacing section 14c, input/output timings of the video data can be characterized as follows. Data interfacing section 14c implements only the input (receiving) operation of the video data because the second provisional data storing section does not have a stored video data during a time interval for loading the video data of a first horizontal line among one subfield to the first provisional data storing section. On the contrary, data interfacing section 14c implements only the output operation of the video data because no video data is supplied from frame memory 14b during a time interval for outputting the video data of a last horizontal line among the subfield to the address electrode driving sections 20 and 22. Accordingly, during the addressing time of one subfield, one final time that the video data is outputted from data interfacing section 14c is behind another final time that the video data is inputted to data interfacing section 14c by a delay-time being taken for an input (or output) of the video data of the one horizontal line. The delay-time is about 3 micro-seconds.
Data interfacing section 14c implements the input and output operations of the video signal under a control of control signals produced by timing control section 16. Accordingly, timing control section 16 is requested to produce the control signals suitable for characteristics of input/output operations of the video data of data interfacing section 14c as above.